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--TOP VIEW--
C-MOS FDC (FLOPPY DISK CONTROLLER)
aS 49 GND at 50 .D 51 w 52 w w53 GND
54 55 56 57 58 59 60 61 62 63 64
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HD63266F (1/3) IL00
VDD (+5V) VDD (+5V)
VDD (+5V) NC
GND GND
NC
NC
NC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD(+5V) GND GND
GND
GND
GND
PIN No. I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I I I I I I I I I -- -- I/O I/O I/O I/O I/O
SIGNAL 8" / 5" XTALSEL RESET E, RD R/W, WR CS DACK RS0 RS1 GND GND D0 D1 D2 D3 D4
PIN No. I/O 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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I/O I/O I/O O O I -- O -- I I I I I I I
SIGNAL
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PIN No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
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SIGNAL TRK0 INDEX RDATA XTAL2 NC NC XTAL1 NC GND GND NC VDD VDD VDD WGATE WDATA
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(VDD = +5V) I/O I I I I -- -- I -- -- -- -- -- -- -- O O PIN No. I/O 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 -- O O O O -- O O O O -- O O O O -- SIGNAL GND STEP HDIR HLOAD HSEL GND DS0 DS1 DS2 DS3 GND MON0 MON1 MON2 MON3 GND
D5 D6 D7 DREQ IRQ DEND GND 1/2EX1 VDD NUM1 NUM2 IFS SFORM INP READY WPRT
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HD63266F (2/3) INPUT 8"/5" CS DACK DEND E, RD IFS INDEX INP NUM1, 2 R/W, WR RDATA READY RESET RS0, 1 SFORM TRKO WPRT XTAL1, 2 XTALSEL OUTPUT 1/2EX1 DREQ DS0-DS3 HDIR HLOAD HSEL IRQ MON0-MON3 STEP WDATA WGATE
12 13 14 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7 1/2 EX1 RESET E, RD R/W, WR CS RS0 RS1 HDIR HLOAD HSEL DS0 DS1 DS2 RDATA INDEX TRKO MON0 MON1 XTALSEL NUM1 NUM2 30 INP 32 WPRT 39 36 XTAL1 XTAL2 1 28 29 31 8"/5" IFS SFORM READY MON2 MON3 60 61 62 63 DS3 51 52 53 55 56 57 58 STEP 50 24 WGATE WDATA 47 48 DREQ 20 IRQ 21
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
DATA TRANSFER RATE SELECT CHIP SELECT DMA ACKNOWLEDGE DMA END ENABLE, READ INTERFACE SELECT INDEX INPUT PORT NOT USER MODE 1, 2 READ/WRITE, WRITE READ DATA READY RESET REGISTER SELECT 0, 1 SELECT FORMAT DATA TRACK 00 WRITE PROTECTED XTAL 1, 2 XTAL SELECT 1/2 EXTAL1 DMA REQUEST DRIVE SELECT 0-3 HEAD DIRECTION HEAD LOAD HEAD SELECT INTERRUPT REQUEST MOTOR ON 0-3 STEP WRITE DATA WRITE GATE
3 4 5 6 8 9
7 22
DACK DEND
35 34 33 2 26 27
INPUT/OUTPUT D0-D7 ; DATA BUS 0-7
HD63266F (3/3)
ROM ADDRESS CONTROL SEEK CONTROL
ALU
TIMER
INTERNAL BUS HOST PROM RAM WRITE CONTROL FDD
HOST INTERFACE
CLOCK GENERATOR
READ CONTROL
VFO
I/O PORT DRIVER, RECEIVER
ALU; ARITHMETIC LOGIC UNIT VFO; VARIABLE FREQUENCY OSCILLATOR

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